CTSD Precision ADCs – Part 5: Digital Data Interface Simplification with Asynchronous Sample Rate Conversion (ASRC)

CTSD Precision ADCs - Part 5: Digital Data Interface Simplification with Asynchronous Sample Rate Conversion (ASRC)

The article series has highlighted the architectural traits of continuous-time sigma-delta (CTSD) analog-to-digital converter (ADC) modulator loops that simplify the signal chain design on the analog input side of the ADC. We now look at simple, innovative ways of interfacing the ADC data to the external digital host performing application-related processing on this data. Digital data output sample rate is a key parameter of an ADC signal chain for any application. However, there are varied requirements on the sample rate that are different for each application. This article introduces a novel on-chip sample rate conversion technique used on a core ADC’s output, allowing signal chain designers to process the ADC digital output data at the desired sample rate for their application.

View the full version of 'CTSD Precision ADCs - Part 5: Digital Data Interface Simplification with Asynchronous Sample Rate Conversion (ASRC),' on the Analog.com website.